Create RISC-V Core using Verilog HDL (3) “Simulation Tools.”

About this project

Hi, I’m currently implementing a RISC-V core using Verilog HDL to deepen my understanding of the CPU. Here is the GitHub of this project.


The goal of today’s post is to make you familiar with the vivado simulation tool. By using this tool, you can debug your circuit more easily.

Create Vivado Project

The first thing you have to do is to create a vivado project for simulations.

$: vivado &

First, you should push “create project” and specify a directory. Then, your project file is created in the directory.

When you see this window, you should push “add files” and specify all of your HDL files, including the test HDL file.

After that, you can push next repeatedly (you don't need to select the specific board if you only use the simulation), and finally, you create a project.

Run Simulation

After you created a project, you may see this kind of window.

Vivado automatically chooses test_cpu as the top module, he is smarter than I thought...

If you push the Run simulation button on the left side, you will get the result as the following picture.

This is the result of the simulation.

Customize simulation

The result is divided into three windows. The most left one shows the hierarchy of your circuit, and if you push the component, you can see the wire of registers inside the components in the center window. The right window shows the wave of each step.

By dragging the components you want to see the waves from the center part and dropping in the right part, you can add them to the simulation configuration. I added the “pc,” “ctr_info,” and “jump_dest” in this example. You can also delete some components by double click.

After you configured your simulation, you should push the run simulation button again. After pushing it, you will be asked whether you create the wave configuration (wcfg files), so please answer yes and create it.

After that, you will see the waves of what you wanted to see as follows.

At the End

The simulation is one of the good tools for debugging circuits. People who control simulations may control debugging, so let’s all do our best in debugging.

I will debug my RISC-V core soon…



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