Create RISC-V Core Using Verilog HDL (4) “Create a core that can execute Fibonacci”

About this project

Hi, I’m currently implementing a RISC-V core using Verilog HDL to deeper understand the CPU. Here is the GitHub of this project. If you are interested, please give me a star.

Today’s version is written in the following link.

yoshi-ki/RISC-V-core

What should I do to execute Fibonacci

Last time, I created a core that can execute add. The only thing I have to do is to implement all of the RISV-V 32i instructions. That is really straightforward and easy to do.

Debug Debug Debug

Implementing instructions is a very simple task, but implementing it without bugs is a difficult task. I used a simulation tool provided by Xilinx. If you are unfamiliar with the tool, look at the link here. Here I list the points I failed in the first implementation.

1. Since the pc increases by 4, there is a discrepancy with the design that increases by 1. To resolve this discrepancy, an arithmetic shift must be performed.
2. mistake in the declaration (length mismatch). I think this kind of mistake should be warned by the compiler…:thinking_face:
3. Sometimes addition is done in unsigned operations. We should declare signed in the case of signed operations.
4. We should avoid writing zero registers. Some operations try to write values in zero registers (for instance jal).
5. We should initialize the stack pointer.

examples)
1. CTR_INFO.pc + ($signed(CTR_INFO.immediate) >>> 2)
2. wire funct3 = (R_type | I_type | S_type | B_type) ? funct3_ : 3'b0;
3. $signed(CTR_INFO.pc) + $signed($signed(CTR_INFO.immediate) >>> 2)

Finally

By debugging above all, I finally finished the implementation of Fibonacci. Next, I will try to do pipeline this design. Thank you for reading!