Create RISC-V Core Using Verilog HDL (5) “Pipeline”
About this project
Hi, I’m currently implementing a RISC-V core using Verilog HDL to deeper understand the CPU. Here is the GitHub of this project. If you are interested, please give me a star.
Today’s version is written in the following link.
What should I do to realize pipelining?
There are three things to do for pipelining.
- Create pipeline registers.
- Prevent the control hazard.
- Do forwarding.
I will explain how to realize them.
Pipeline registers
Pipeline registers are easy to make because the control_info in the last implementation is the same as the pipeline registers. The control_info (pipeline registers) holds the information about the instructions that are executed now. The program counter and destination registers are good examples.
Control hazard
The second thing we have to care about is the control hazard. The control hazard occurs when the pipeline makes wrong decisions on branch prediction. To prevent it, we have to stop the pipeline when we encounter the branch instructions. I created the flag that represents the branch instructions and stored it in the pipeline registers. The processor stalls two cycles and then it starts execution again.
Forwarding
The third thing we have to care about is the “read-after-write.” The read-after-write consistency is the ability to view changes (read data) right after making those changes (write data). We have to maintain it. One way to maintain it is to forward the result in the write stage into the execution stage. I prevented read-after-write in this way.
Debug Debug Debug
The debug is a little easier than creating state machine processors because we already have an existing correct wave by the state machine processors!
Finally
I finally created the RISC-V core with 4 line pipelines. This is a good experience to deepen my understanding of processors!
I’ve written a step-by-step guide to implement RISC-V core throughout this blog. I hope that someday someone who wants to learn about processors will see this and break it down into small goals that beginners can work towards.
